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www.fairchildsemi.com features ? 10-bit resolution ? 80, 50, and 30 megapixels per second ? sync and blank controls ? sync on green d/a output ? 1.0v p-p video into 37.5 w or 75 w load ? enhancement of adv7122 C internal bandgap voltage reference C double-buffered data for low distortion ? ttl-compatible inputs ? low glitch energy ? single +3.3 volt 5% power supply applications ? video signal conversion C rgb C yc b c r C composite, y, c ? multimedia systems ? image processing ? true-color graphics systems (1 billion colors) ? broadcast television equipment ? high-de?nition television (hdtv) equipment ? direct digital synthesis description the TMC3033 is a high-speed triple 10-bit d/a converter especially suited for video and graphics applications. it offers 10-bit resolution, ttl-compatible inputs, low power consumption, and requires only a single +3.3 volt 5% power supply. it has single-ended current outputs, sync and blank control inputs, and a separate current source for adding sync pulses to the green d/a converter output. it is ideal for generating analog rgb from digital rgb and driving computer display and video monitors. three speed grades are available: 30, 50, and 80 msps. the TMC3033 triple d/a converter is available in a 44-lead plastic j-leaded plcc and 48-lead plastic lqfp package. it is fabricated on a sub-micron cmos process with perfor- mance guaranteed from 0 c to 70 c. block diagram 10 bit d/a converter 10 bit d/a converter 10 bit d/a converter 10 g 9-0 blank sync clk io g io b io r v ref r ref comp 65-3003-01 +1.235v ref 10 b 9-0 10 r 9-0 TMC3033 triple video d/a converter 10 bit, 80 msps rev. 1.0.0
TMC3033 product specification 2 functional description the TMC3033 is a lo w-cost triple 10-bit cmos d/a con v erter designed to directly dri v e computer cr t displays and video transmission lines at pix el rates of up to 80 msps. it comprises three identical 10-bit d/a con v erters with re gistered data inputs, common clock, and internal v oltage reference. an independent current source allo ws sync to be added to the green d/a con v erter output. digital inputs all digital inputs are ttl- compatible. data are re gistered on the rising edge of the clk signal. the analog output changes t do after the rising edge of clk. there is one stage of pipeline delay on the chip. the guaranteed clock rates of the TMC3033 are 80, 50, and 30 mhz. sync and blank sync and blank inputs control the output le v el (figure 1 and t able 1) of the d/a con v erters during cr t retrace interv als. blank forces the d/a outputs to the blanking le v el while sync turns of f a separate current source which is connected to the green d/a con v erter . this connection adds a 40 ire sync pulse to the d/a output and brings that d/a output to 0.0 v olts during the sync tip. sync and blank are re gistered on the rising edge of clk. blank g ates the d/a inputs and sets the pedestal v oltage. if blank = high, the d/a inputs are added to a pedestal which of fsets the current output. if blank = lo w , data inputs and the pedestal are disabled. figure 1. nominal output levels data: 660 mv max. 65-3003-02 pedestal: 54 mv sync: 286 mv d/a outputs each d/a output is a current source. t o obtain a v oltage out- put a resistor must be connected to ground. output v oltage of the d/a con v erters depends upon this resistor , the reference v oltage, and the v alue of the g ain-setting resistor connected between r ref and gnd. normally , a source termination resistor of 75 ohms is con- nected between the d/a current output pin and gnd near the d/a con v erter . a 75 ohm coaxial cable may then be con- nected with another 75 ohm termination resistor at the f ar end of the cable. this double termination presents the d/a con v erter with a net resisti v e load of 37.5 ohms. the TMC3033 may also be operated with a single 75 ohm terminating resistor . t o lo wer the output v oltage swing to the desired range, the v alue of the resistor on r ref should be increased. v olta g e ref erence the TMC3033 has an internal bandg ap v oltage reference of +1.235 v olts. an e xternal v oltage reference may be connected to the v ref pin, o v erriding the internal v oltage reference. all three d/a con v erters are dri v en from the same reference. a 0.1 m f capacitor must be connected between the comp pin and v dd to stabilize internal bias circuitry and ensure lo w-noise operation. p o wer and gr ound the TMC3033 d/a con v erter requires a single +3.3 v olt po wer supply . the analog (v dd ) po wer supply v oltage should be decoupled to gnd to reduce po wer supply induced noise. 0.1 m f decoupling capacitors should be placed as close as possible to the po wer pins. the high sle w- rate of digital data mak es capaciti v e coupling to the outputs of an y d/a con v erter a potential problem. since the digital signals contain high- frequenc y components of the clk signal, as well as the video output signal, the resulting data feedthrough often looks lik e harmonic distor - tion or reduced signal- to- noise performance. all ground pins should be connected to a common solid ground plane for best performance.
product specification TMC3033 3 t ab le 1. output v olta g e ver sus input code , sync , and blank v ref = 1.235 v , r ref = 572 w , r l = 37.5 w pin assignments rgb 9-0 (msb...lsb) red and blue d/as green d/a sync blank v out sync blank v out 11 1111 1111 x 1 0.7140 1 1 1.0000 11 1111 1110 x 1 0.7134 1 1 0.9994 11 1111 1101 x 1 0.7127 1 1 0.9987 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 10 0000 0000 x 1 0.3843 1 1 0.6703 01 1111 1111 x 1 0.3837 1 1 0.6697 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 00 0000 0010 x 1 0.0553 1 1 0.3413 00 0000 0001 x 1 0.0546 1 1 0.3406 00 0000 0000 x 1 0.0540 1 1 0.3400 xx xxxx xxxx x 0 0.0000 1 0 0.2860 xx xxxx xxxx x 0 0.0000 0 0 0.0000 g 1 g 2 g 3 g 4 g 5 g 6 g 7 g 8 g 9 blank sync r ref v ref comp io r io g v dd v dd io b gnd gnd clk g 0 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 v dd b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 TMC3033 g 1 g 2 g 3 g 4 g 5 g 6 g 7 g 8 g 9 blank v dd r 2 r 1 nc r ref v ref comp io g io r o v dd v dd io b gnd gnd nc g 0 r 9 r 8 r 7 r 6 r 5 r 4 r 3 nc b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 8 b 7 nc 1 2 3 4 5 6 7 8 9 10 sync 11 12 36 35 34 33 32 31 30 29 28 27 clock 26 25 13 14 15 16 17 18 19 20 21 22 b 9 23 24 48 47 46 45 44 43 42 41 40 39 r 0 38 37 TMC3033 lqfp plcc
TMC3033 product specification 4 pin descriptions pin name pin number v alue description plcc lqfp cloc k and pix el i/o clk 29 26 ttl clock. the clock input is ttl- compatible and all pixel data is registered on the rising edge of clk. it is recommended that clk be driven by a dedicated ttl buffer to avoid reflection induced jitter, overshoot, and undershoot. r 9-0 5, 4, 3, 2, 1, 44, 43, 42, 41, 40 47, 46, 45, 44, 43, 42, 41, 40, 39, 38, 37 ttl red pixel data inputs. the red digital input is ttl- compatible and registered on the rising edge of clk. g 9-0 15, 14, 13, 12, 11, 10, 9, 8, 7, 6 48, 9, 8, 7, 6, 5, 4, 3, 2, 1 ttl green pixel data inputs. the green digital input is ttl- compatible and registered on the rising edge of clk. b 9-0 28, 27, 26, 25, 24, 23, 22, 21, 20, 19 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 ttl blue pixel data inputs. the blue digital input is ttl- compatible and registered on the rising edge of clk. contr ols sync 17 11 ttl sync pulse input. bringing sync low, turns off a 40 ire (7.62 ma) current source which forms a sync pulse on the green d/a converter output. sync is registered on the rising edge of clk along with pixel data and has the same pipeline latency as blank and pixel data. sync does not override any other data and should be used only during the blanking interval. since this is a single-supply d/a and all signals are positive-going, sync is added to the bottom of the green d/a range. so turning sync off means turning the current source on. when a sync pulse is desired, the current source is turned off. if the system does not require sync pulses from the green d/a converter, sync should be connected to gnd. blank 16 10 ttl blanking input. when blank is low, pixel inputs are ignored and the d/a converter outputs are driven to the blanking level. blank is registered on the rising edge of clk and has the same pipeline latency as sync . video outputs io r 36 33 0.714 vp- p red d/a output. the current source outputs of the d/a converters are capable of driving rs- 343a/smpte-170m compatible levels into doubly- terminated 75 ohm lines. io g 35 32 1 v p- p green d/a output. the current source outputs of the d/a converters are capable of driving rs- 343a/smpte-170m compatible levels into doubly- terminated 75 ohm lines. sync pulses may be added to the green d/a output. io b 32 29 0.714 vp- p blue d/a output. the current source outputs of the d/a converters are capable of driving rs- 343a/smpte-170m compatible levels into doubly- terminated 75 ohm lines.
product specification TMC3033 5 equiv alent cir cuits figure 2. equivalent digital input circuit figure 3. equivalent analog output circuit v olta g e ref erence v ref 38 35 +1.235 v voltage reference output/input. an internal voltage source of +1.235 volts is output on this pin. an external +1.235 volt reference may be applied here which overrides the internal reference. decoupling v ref to gnd with a 0.1 m f ceramic capacitor is required. r ref 39 36 572 w current- setting resistor. the full- scale output current of each d/a converter is determined by the value of the resistor connected between r ref and gnd. the nominal value for r ref is found from: r ref = 9.1( v ref /i fs ), but is optimized to be 572 w . i fs is the full-scale (white) output current (in amps) from an output without sync. sync current is 0.4 * i fs . d/a full-scale (white) current may also be calculated from: i fs = v fs / r l where v fs is the white voltage level and r l is the total resistive load (in ohms) on each d/a converter. v fs is the blank to full-scale voltage. comp 37 34 0.1 m f compensation capacitor. a 0.1 m f ceramic capacitor must be connected between comp and v dd to stabilize internal bias circuitry. p o wer and gr ound v dd 18, 33, 34 12, 30, 31 +3.3 v power supply gnd 30, 31 27, 28 0.0 v ground pin descriptions (contin ued) pin name pin number v alue description plcc lqfp digital input v dd p n 27014c gnd n p out gnd 27013b v dd v dd
TMC3033 product specification 6 equiv alent cir cuits (contin ued) figure 4. equivalent analog input circuit absolute maxim um ratings (be y ond which the de vice ma y be damaged) 1 notes: 1. functional operation under any of these conditions is not implied. performance and reliability are guaranteed only if operating conditions are not exceeded. 2. applied voltage must be current limited to specified range. 3. forcing voltage must be limited to specified range. 4. current is specified as conventional current flowing into the device. p arameter min t yp max unit p o wer suppl y v olta g e v dd (measured to gnd) -0.5 7.0 v inputs applied voltage (measured to gnd) 2 -0.5 v dd + 0.5 v forced current 3,4 -10.0 10.0 ma outputs applied voltage (measured to gnd) 2 -0.5 v dd + 0.5 v forced current 3,4 -60.0 60.0 ma short circuit duration (single output in high state to ground) in? nite second t emperature operating, ambient -20 110 c junction 150 c lead soldering (10 seconds) 300 c vapor phase soldering (1 minute) 220 c storage -65 150 c p gnd 27012b r ref v ref v dd p
product specification TMC3033 7 operating conditions electrical characteristics notes: 1. values shown in typ column are typical for v dd = +3.3v and t a = 25 c. 2. minimum/maximum values with v dd = max and t a = min. 3. v ref = 1.235v, r load = 37.5 w , r ref = 572 w p arameter min nom max units v dd power supply voltage 3.135 3.3 3.465 v f s conversion rate TMC3033-30 30 msps TMC3033-50 50 msps TMC3033-80 80 msps t pwh clk pulsewidth, high 5.2 ns t pwl clk pulsewidth, low 5.2 ns t s input data setup time 3.6 ns t h input date hold time 2 ns v ref reference voltage, external 1.0 1.235 1.5 v c c compensation capacitor 0.1 m f r l output load 37.5 w v ih input voltage, logic high 2.0 v dd v v il input voltage, logic low gnd 0.8 v t a ambient temperature, still air 0 70 c p arameter conditions 3 min t yp 1 max units i dd power supply current 2 v dd = max TMC3033-30 90 ma TMC3033-50 95 TMC3033-80 132 pd total power dissipation 2 v dd = max TMC3033-30 300 mw TMC3033-50 315 TMC3033-80 435 r o output resistance 100 k w c o output capacitance i out = 0ma 30 pf i ih input current, high v dd = max, v in = 2.4v -1 m a i il input current, low v dd = max, v in = 0.4v 1 m a i ref v ref input bias current 0 100 m a v ref reference voltage output 1.235 v v oc output compliance referred to v dd -0.4 0 +1.5 v c di digital input capacitance 4 10 pf
TMC3033 product specification 8 switc hing characteristics notes: 1. values shown in typ column are typical for v dd = +3.3v and t a = 25 c. 2. v ref = 1.235v, r load = 37.5 w , r ref = 572 w . system p erf ormance characteristics notes: 1. values shown in typ column are typical for v dd = +3.3v and t a = 25 c. 2. v ref = 1.235v, r load = 37.5 w , r ref = 572 w . timing dia gram p arameter conditions 2 min t yp 1 max units t d clock to output delay v dd = min 10 15 ns t skew output skew 1 2 ns t r output risetime 10% to 90% of full scale 3 4 ns t f output falltime 90% to 10% of full scale 3 4 ns t set output settling time to 3%/fs 15 ns p arameter conditions 2 min t yp 1 max units e li integral linearity error v dd , v ref = nom 0.1 0.25 %/fs e ld differential linearity error v dd , v ref = nom 0.1 0.25 %/fs e dm dac to dac matching v dd , v ref = nom 7 10 % v of output offset current v dd = max, r, g, b = 000h 20 ma psr power supply rejection 0.05 %/% clk pixel data & controls output 65-3003-03 datan datan+1 datan+2 t pwl t s t h 50% 3%/fs 90% 10% t d t set t f t r t pwh 1/f s
product specification TMC3033 9 applications discussion figure 4 illustrates a typical TMC3033 interf ace circuit. in this e xample, an optional 1.2 v olt bandg ap reference is connected to the v ref output, o v erriding the internal v olt- age reference source. gr ounding it is important that the TMC3033 po wer supply is well- re gulated and free of high- frequenc y noise. careful po wer supply decoupling will ensure the highest quality video sig- nals at the output of the circuit. the TMC3033 has separate analog and digital circuits. t o k eep digital system noise from the d/a con v erter , it is recommended that po wer supply v oltages (v dd ) come from the system analog po wer source and all ground connections (gnd) be made to the analog ground plane. po wer supply pins should be indi vidu- ally decoupled at the pin. printed cir cuit boar d la y out designing with high-performance mix ed-signal circuits demands printed circuits with ground planes. ov erall system performance is strongly in? uenced by the board lay- out. capaciti v e coupling from digital to analog circuits may result in poor d/a con v ersion. consider the follo wing suggestions when doing the layout: 1. k eep the critical analog traces (v ref , i ref , comp , io r , io g , io b ) as short as possible and as f ar as possi- ble from all digital signals. the TMC3033 should be located near the board edge, close to the analog output connectors. 2. the po wer plane for the TMC3033 should be separate from that which supplies the digital circuitry . a single po wer plane should be used for all of the v dd pins. if the po wer supply for the TMC3033 is the same as that of the system's digital circuitry , po wer to the TMC3033 should be decoupled with 0.1 m f and 0.01 m f capacitors and isolated with a ferrite bead. 3. the ground plane should be solid, not cross-hatched. connections to the ground plane should ha v e v ery short leads. 4. if the digital po wer supply has a dedicated po wer plane layer , it should not be placed under the TMC3033, the v oltage reference, or the analog outputs. capaciti v e cou- pling of digital po wer supply noise from this layer to the TMC3033 and its related analog circuitry can ha v e an adv erse ef fect on performance. 5. clk should be handled carefully . jitter and noise on this clock will de grade performance. t erminate the clock line carefully to eliminate o v ershoot and ringing. related pr oducts ? tmc3503 t riple 8-bit 80 msps d/a con v erters ? tmc1175a 40 msps cmos 8-bit a/d con v erter ? tmc1275 40 msps cmos 8-bit a/d con v erter ? tmc22091, tmc22191 digital v ideo encoders ? tmc2242c/tmc2243/tmc2246a v ideo filters ? tmc2249a digital mix er ? tmc2250a matrix multiplier ? tmc2272a colorspace con v erter ? tmc2302 image manipulation sequencer ? tmc2340a digital synthesizer ? tmc2081 digital v ideo mix er figure 4. typical interface circuit 65-3033-04 r 9-0 g 9-0 b 9-0 +3.3v 0.1 f 10 f v dd gnd TMC3033 triple 10-bit d/a converter clk sync blank red pixel input green pixel input blue pixel input clock sync blank comp v ref r ref +3.3v 0.1 f 0.1 f 572 3.3k lm185-1.2 (optional) io r io g io b 75 75 75 75 75 75 z o =75 z o =75 z o =75 red green blue
TMC3033 product specification 10 mec hanical dimensions C 44-lead plcc p ac ka g e d e e a .165 .180 4.19 4.57 symbol inches min. max. min. max. millimeters notes e1 j d1 a a1 a2 b b1 d3/e3 j ?c ccc c lead coplanarity a1 .090 .120 2.29 3.05 a2 .020 .51 b .013 .021 .33 .53 d/e .685 .695 17.40 17.65 d1/e1 .650 .656 16.51 16.66 d3/e3 .500 bsc 12.7 bsc e .050 bsc 1.27 bsc j .042 .056 1.07 1.42 2 3 nd/ne 11 11 n 44 44 ccc .004 0.10 b1 .026 .032 .66 .81 notes: 1. 2. 3. all dimensions and tolerances conform to ansi y14.5m-1982 corner and edge chamfer (j) = 45 dimension d1 and e1 do not include mold protrusion. allowable protrusion is .101" (.25mm)
product specification TMC3033 11 mec hanical dimensions C 48-lead lqfp p ac ka g e d e1 e e pin 1 identifier b base plane seating plane see lead detail c 0.063" ref (1.60mm) l -c- ccc c lead coplanarity a2 a a1 a a .055 .063 1.40 1.60 symbol inches min. max. min. max. millimeters notes a1 .001 .005 .05 .15 .057 1.45 a2 .053 1.35 b .006 .010 .17 .27 d/e d1/e1 .019 bsc .346 .362 8.8 9.2 .268 .284 6.8 7.2 .50 bsc e l .017 .029 .45 .75 6 4 5 2 7 8 a 0 7 0 7 n 48 48 12 12 nd ccc .004 0.08 notes: 1. 2. 3. 4. 5. 6. 7. 8. d1 all dimensions and tolerances conform to ansi y14.5m-1982. dimensions "d1" and "e1" do not include mold protrusion. allowable protrusion is 0.25mm per side. d1 and e1 are maxim um plastic body size dimensions including mold mismatch. pin 1 identifier is optional. dimension nd: number of terminals. dimension nd: number of terminals per package edge. "l" is the length of terminal for soldering to a substrate. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. to be determined at seating place ?
TMC3033 product specification 3/3/99 0.0m 001 stock#ds30003033 1999 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com or dering inf ormation pr oduct number con ver sion rate (msps) t emperature rang e screening p ac ka g e p ac ka g e marking TMC3033r2c30 30 msps t a = 0 c to 70 c commercial 44-lead plcc 3033r2c30 TMC3033r2c50 50 msps t a = 0 c to 70 c commercial 44-lead plcc 3033r2c50 TMC3033r2c80 80 msps t a = 0 c to 70 c commercial 44-lead plcc 3033r2c80 TMC3033krc30 30 msps t a = 0 c to 70 c commercial 48-lead lqfp 3033krc30 TMC3033krc50 50 msps t a = 0 c to 70 c commercial 48-lead lqfp 3033krc50 TMC3033krc80 80 msps t a = 0 c to 70 c commercial 48-lead lqfp 3033krc80

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